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CY7C109BN CY7C1009BN
128K x 8 Static RAM
Features
* High speed -- tAA = 12 ns * Low active power -- 495 mW (max. 12 ns) * Low CMOS standby power -- 55 mW (max.) 4 mW * 2.0V Data Retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE options
Functional Description[1]
The CY7C109BN/CY7C1009BN is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C109BN is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009BN is available in a 300-mil-wide SOJ package. The CY7C1009BN and CY7C109BN are functionally equivalent in all other respects.
Logic Block Diagram
Pin Configurations
SOJ Top View
NC A16 A14 A12
A7 A6 A5 A4 A3 A2 A1
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8
I/O1
ROW DECODER
I/O2
SENSE AMPS 512 x 256 x 8 ARRAY
I/O0 I/O1 I/O2 GND A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
I/O3 I/O4 I/O5
CE1 CE2 WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
TSOP I Top View (not to scale)
Note: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-06430 Rev. **
A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 1, 2006
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CY7C109BN CY7C1009BN
Selection Guide
7C109B-12 7C1009B-12 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current L 12 90 10 2 7C109B-15 7C1009B-15 15 80 10 2 7C109B-20 7C1009B-20 20 75 10 2 Unit ns mA mA mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[2] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ....................................-0.5V to VCC + 0.5V DC Input Voltage[2] .................................-0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
7C109BN-12 7C1009BN-12 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 Description Test Conditions Min. 2.4 0.4 2.2 -0.3 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC -1 -5 VCC + 0.3 0.8 +1 +5 -300 90 45 2.2 -0.3 -1 -5 Max. Output HIGH Voltage VCC = Min., IOH = -4.0 mA Output LOW Voltage VCC = Min., IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current 7C109BN-15 7C1009BN-15 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 80 40 2.2 -0.3 -1 -5 Max. 7C109BN-20 7C1009BN-20 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 75 30 Max. Unit V V V V A A mA mA mA
Max. VCC, CE1 > VIH Automatic CE Power-Down Current or CE2 < VIL, VIN > VIH or --TTL Inputs VIN < VIL, f = fMAX Automatic CE Max. VCC, Power-Down Current CE1 > VCC - 0.3V, or CE2 < 0.3V, --CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 L
ISB2
10 2
10 2
10 2
mA mA
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 9 8 Unit pF pF
Notes: 2. Minimum voltage is -2.0V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters.
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CY7C109BN CY7C1009BN
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255 R1 480 R1 480 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255 GND 3 ns 3.0V 90% 10% 90% 10% 3 ns ALL INPUT PULSES
Equivalent to:
THEVENIN EQUIVALENT 167 1.73V OUTPUT
Switching Characteristics[5] Over the Operating Range
7C109BN-12 7C1009BN-12 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6, 7] CE1 LOW to Low Z, CE2 HIGH to Low Z[7] CE1 HIGH to High Z, CE2 LOW to High Z[6, 7] 0 12 CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down Write Cycle Time[9] CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z[6, 7] 12 10 10 0 0 10 7 0 3 6 3 6 0 15 0 6 3 7 0 20 3 12 6 0 7 3 8 12 12 3 15 7 0 8 15 15 3 20 8 20 20 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C109BN-15 7C1009BN-15 Min. Max. 7C109BN-20 7C1009BN-20 Min. Max. Unit
Write Cycle[8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE 15 12 12 0 0 12 8 0 3 7 20 15 15 0 0 12 10 0 3 8 ns ns ns ns ns ns ns ns ns ns
Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Data Retention Characteristics Over the Operating Range (Low Power version only)
Parameter VDR ICCDR tCDR tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions No input may exceed VCC + 0.5V VCC = VDR = 2.0V, CE1 > VCC - 0.3V or CE2 < 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Min. 2.0 150 0 200 Max Unit V A ns s
Data Retention Waveform
DATA RETENTION MODE VCC 4.5V tCDR CE VDR > 2V 4.5V tR
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Notes: 10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
Document #: 001-06430 Rev. **
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Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 15 tHZOE DATAIN VALID tHD
Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-06430 Rev. **
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Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[14]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tSD DATA I/O NOTE 15 tHZWE DATA VALID tLZWE tHD tPWE tHA
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0-I/O7 High Z High Z Data Out Data In High Z Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Document #: 001-06430 Rev. **
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CY7C109BN CY7C1009BN
Ordering Information
Speed (ns) 12 Ordering Code CY7C109BN-12VC CY7C1009BN-12VC CY7C109BN-12ZC CY7C109BN-12ZXC 15 CY7C109BNL-15VC CY7C109BN-15VC CY7C1009BN-15VC CY7C109BN-15ZC CY7C109BN-15ZXC CY7C109BN-15VI CY7C1009BN-15VI 20 CY7C109BN-20VC CY7C1009BN-20VC CY7C109BN-20VI CY7C109BN-20ZC CY7C109BN-20ZXC Package Diagram 51-85032 51-85031 51-85056 51-85056 51-85032 51-85032 51-85031 51-85056 51-85056 51-85032 51-85031 51-85032 51-85031 51-85032 51-85056 51-85056 Package Type 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead TSOP Type I (Pb-free) 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead TSOP Type I (Pb-free) 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (300-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead TSOP Type I 32-Lead TSOP Type I (Pb-free) Industrial Commercial Commercial Industrial Commercial Operating Range Commercial
Please contact local sales representative regarding availability of these parts
Package Diagrams
PIN 1 I.D
28-Lead (400-Mil) Molded SOJ (51-85032)
14
1
.395 .405
.435 .445
DIMENSIONS IN INCHES
MIN. MAX.
15
28
.720 .730 SEATING PLANE .128 .148 .050 TYP. .015 .020 .026 .032
0.004
.007 .013 .360 .380
51-85032-*B
.025 MIN.
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CY7C109BN CY7C1009BN
Package Diagrams (continued)
NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX.
28-Lead (300-Mil) Molded SOJ (51-85031)
PIN 1 ID
14 1
DETAIL A EXTERNAL LEAD DESIGN
0.291 0.300
0.330 0.350 0.013 0.019
OPTION 1 OPTION 2
0.026 0.032 0.014 0.020
15
28
0.697 0.713 0.120 0.140 0.050 TYP.
SEATING PLANE
0.007 0.013
0.004
A
0.025 MIN.
0.262 0.272
51-85031-*C
32-Lead TSOP I (8x20 mm) (51-85056)
51-85056-*D
All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06430 Rev. ** Page 8 of 9
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY7C109BN/CY7C1009BN 128K x 8 Static RAM Document Number: 001-06430 REV. ** ECN NO. 423847 Issue Date See ECN Orig. of Change NXR Description of Change New Data Sheet
Document #: 001-06430 Rev. **
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